Renesas H8S Series Hardware Manual page 383

Bit 7
Channel IOD3
3 0
1
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is
invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Bit 6 Bit 5 Bit 4
IOD2 IOD1 IOD0 Description
0 0 0 TGR3D is Output disabled
output
1
compare
0
1
register*
1
1 0 0
1
1 0
1
0 0 0 TGR3D is
input
1
capture
×
1
register*
× ×
1
Initial output is 0 0 output at compare match
output
1 output at compare match
2
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCD3 pin
2 Input capture at both edges
Capture input Input capture at TCNT4
source is channel count-up/count-down*
4/count clock
Rev.6.00 Oct.28.2004 page 355 of 1016
(Initial value)
1
×: Don't care
REJ09B0138-0600H