Renesas H8S Series Hardware Manual page 726

(5) Timing of On-Chip Supporting Modules
Table 22-8 lists the timing of on-chip supporting modules.
Table 22-8 Timing of On-Chip Supporting Modules
= 5.0 V ± 10%, AV
Conditions: V
CC
V = AV
SS
T = –40 to +85°C (wide-range specifications)
a
Item
PORT Output data delay time t
Input data setup time
Input data hold time
PPG Pulse output delay time t
TPU Timer output delay time t
Timer input setup time
Timer clock input setup
time
Timer clock
pulse width
TMR Timer output delay time t
Timer reset input setup
time
Timer clock input setup
time
Timer clock
pulse width
SCI Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay
time
Receive data setup
time (synchronous)
Receive data hold
time (synchronous)
A/D Trigger input setup
con- time
verter
Rev.6.00 Oct.28.2004 page 698 of 1016
REJ09B0138-0600H
= 5.0 V ± 10%, V
CC
= 0 V, ø = 10 to 20 MHz, T
SS
Symbol
PWD
t
PRS
t
PRH
POD
TOCD
t
TICS
t
TCKS
Single t
TCKWH
edge
Both t
TCKWL
edges
TMOD
t
TMRS
t
TMCS
Single t
TMCWH
edge
Both t
TMCWL
edges
Asynchro- t
Scyc
nous
Synchro-
nous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
= 4.5 V to AV ,
ref CC
= –20 to +75°C (regular specifications),
a
Condition
Min Max
— 50
30 —
30 —
— 50
— 50
30 —
30 —
1.5 —
2.5 —
— 50
30 —
30 —
1.5 —
2.5 —
4 —
6 —
0.4 0.6
— 1.5
— 1.5
— 50
50 —
50 —
30 —
Test
Unit Conditions
ns Figure 22-22
ns Figure 22-23
ns Figure 22-24
ns Figure 22-25
t
cyc
ns Figure 22-26
ns Figure 22-28
ns Figure 22-27
t
cyc
t Figure 22-29
cyc
t
Scyc
t
cyc
ns Figure 22-30
ns
ns
ns Figure 22-31