Basic Timing - Renesas H8S Series Hardware Manual

6.4.4

Basic Timing

8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access
space is accessed, the upper half (D
The LWR pin is fixed high. Wait states cannot be inserted.
Rev.6.00 Oct.28.2004 page 128 of 1016
REJ09B0138-0600H
to D ) of the data bus is used.
15 8
ø
Address bus
CSn
AS
RD
D to D
Read
15 8
D to D
7 0
HWR
LWR
Write
D to D
15 8
D to D
7 0
Note: n = 0 to 7
Figure 6-6 Bus Timing for 8-Bit 2-State Access Space
Bus cycle
T T
1 2
Valid
Invalid
High
Valid
High impedance