Register Configuration; Register Descriptions; System Control Register (Syscr) - Renesas H8S Series Hardware Manual

5.1.4

Register Configuration

Table 5-2 summarizes the registers of the interrupt controller.
Table 5-2 Interrupt Controller Registers
Name
System control register
IRQ sense control register H
IRQ sense control register L
IRQ enable register
IRQ status register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt priority register I
Interrupt priority register J
Interrupt priority register K
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
5.2

Register Descriptions

5.2.1

System Control Register (SYSCR)

Bit : 7
—
Initial value : 0
R/W : R/W
Note: * R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398.
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR).
SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Abbreviation
SYSCR
ISCRH
ISCRL
IER
ISR
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
6 5 4
— INTM1 INTM0
0 0 0
— R/W R/W
R/W Initial Value
R/W H'01
R/W H'00
R/W H'00
R/W H'00
2
R/(W)* H'00
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
R/W H'77
3 2
NMIEG — —
0 0
R/W —* R/W
1
Address*
H'FF39
H'FF2C
H'FF2D
H'FF2E
H'FF2F
H'FEC4
H'FEC5
H'FEC6
H'FEC7
H'FEC8
H'FEC9
H'FECA
H'FECB
H'FECC
H'FECD
H'FECE
1 0
RAME
0 1
R/W
Rev.6.00 Oct.28.2004 page 83 of 1016
REJ09B0138-0600H