Renesas H8S Series Hardware Manual page 877

CRB—DTC Transfer Count Register B
Bit
Initial value
Read/Write
TCR3—Timer Control Register 3
Bit
Initial value
Read/Write
:
15 14 13 12
:
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:
— — — —
Specifies the number of DTC block data transfers
: 7 6
CCLR2 CCLR1 CCLR0
: 0 0
: R/W R/W R/W
Counter Clear
0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture *
1 0 TCNT cleared by TGRD compare match/input capture *
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
Notes: 1. Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
H'F800—H'FBFF
11 10 9 8 7
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— — — — —
H'FE80
5 4 3
CKEG1 CKEG0 TPSC2
0 0 0
R/W R/W
Timer Prescaler
0 0
1
1 0
1
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
DTC
6 5 4 3 2
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— — — — —
TPU3
2 1 0
TPSC1 TPSC0
0 0 0
R/W R/W R/W
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
0 External clock: counts on TCLKA pin input
1 Internal clock: counts on ø/1024
0 Internal clock: counts on ø/256
1 Internal clock: counts on ø/4096
1
2
2
1
Rev.6.00 Oct.28.2004 page 849 of 1016
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