Renesas H8S Series Hardware Manual page 539

• Simultaneous serial data transmission and reception (clocked synchronous mode)
Figure 14-20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive operations.
No
No
No
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE and RE bits to 0,
then set both these bits to 1 simultaneously.
Figure 14-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Initialization
Start transmission/reception
Read TDRE flag in SSR
TDRE= 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read ORER flag in SSR
ORER= 1
No
Read RDRF flag in SSR
RDRF= 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
All data received?
Yes
Clear TE and RE bits in SCR to 0
<End>
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to
0. Transmission/reception cannot be
Yes
resumed if the ORER flag is set to
[3]
1.
Error processing
SCI status check and receive data
[4]
read:
Read SSR and check that the
[4]
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
[5]
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request and
data is written to TDR. Also, the
RDRF flag is cleared automatically
when the DMAC or DTC is activated
by a receive data full interrupt (RXI)
request and the RDR value is read.
Rev.6.00 Oct.28.2004 page 511 of 1016
REJ09B0138-0600H