SCR0—Serial Control Register 0
Bit
:
Initial value
:
Read/Write
:
Transmit Interrupt Enable
0
1
Rev.6.00 Oct.28.2004 page 914 of 1016
REJ09B0138-0600H
7
6
5
TIE
RIE
TE
0
0
0
R/W
R/W
R/W
Receive Enable
0
1
Transmit Enable
0
Transmission disabled
1
Transmission enabled
Receive Interrupt Enable
0
Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request disabled
1
Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request enabled
Transmit data empty interrupt (TXI) requests disabled
Transmit data empty interrupt (TXI) requests enabled
H'FF7A
4
3
2
1
RE
MPIE
TEIE
CKE1
0
0
0
0
R/W
R/W
R/W
R/W
Clock Enable
0
0
1
1
0
1
Notes:
1. Outputs a clock of the same frequency as the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
Transmit End Interrupt Enable
0
Transmit end interrupt (TEI) request disabled
1
Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable
0
Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When MPB= 1 data is received
1
Multiprocessor interrupts enabled
Receive data full interrupt (RXI) requests, receive error interrupt
(ERI) requests, and setting of the RDRF, FER, and ORER flags
in SSR are disabled until data with the multiprocessor bit set to
1 is received
Reception disabled
Reception enabled
SCI0
0
CKE0
0
R/W
Asynchronous
Internal clock/SCK pin functions
as I/O port
mode
Internal clock/SCK pin functions
Synchronous
as serial clock output
mode
Asynchronous
Internal clock/SCK pin functions
mode
as clock output*
Internal clock/SCK pin functions
Synchronous
as serial clock output
mode
Asynchronous
External clock/SCK pin functions
2
mode
as clock input*
Synchronous
External clock/SCK pin functions
mode
as serial clock input
Asynchronous
External clock/SCK pin functions
mode
as clock input*
2
Synchronous
External clock/SCK pin functions
mode
as serial clock input
1