Renesas H8S Series Hardware Manual page 255

Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size
single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
Address bus
Figure 7-30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer
(write) is performed from an external device to external 8-bit, 2-state access space.
ø
Address bus
HWR
LWR
DACK
TEND
Figure 7-30 Example of Single Address Mode (Word Write) Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the
bus is released one or more bus cycles are inserted by the CPU or DTC.
DMA write
ø
HWR
LWR
DACK
TEND
Bus Bus
release release
Figure 7-29 Example of Single Address Mode (Byte Write) Transfer
DMA write
Bus
release
DMA write DMA write
Bus
release
DMA write
Bus
release release
DMA
DMA write dead
Bus Last transfer Bus
release cycle release
DMA
DMA write
dead
Bus Last transfer
cycle
Rev.6.00 Oct.28.2004 page 227 of 1016
Bus
release
REJ09B0138-0600H