Pwm Modes - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2

overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and

TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are

transferred to TGR1A, and the lower 16 bits to TGR2A.

Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, and phase

counting mode has been designated for channel 2.

TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level

in response to compare match of each TGR.

Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels

can be designated for PWM mode independently. Synchronous operation is also possible.

There are two PWM modes, as described below.

• PWM mode 1

Figure 10-22 Example of Cascaded Operation (1)

Figure 10-23 Example of Cascaded Operation (2)

Rev.6.00 Oct.28.2004 page 383 of 1016

REJ09B0138-0600H