Renesas H8S Series Hardware Manual page 776

ø
A to A
23
CS7 to CS0
AS
RD
(read)
D to D
15
(read)
HWR, LWR
(write)
D to D
15
(write)
DACK0, DACK1
Figure 22-83 DMAC Single Address Transfer Timing (Three-State Access)
Rev.6.00 Oct.28.2004 page 748 of 1016
REJ09B0138-0600H
T
1
0
0
0
t
DACD1
ø
t
TED
TEND0, TEND1
Figure 22-84 DMAC TEND Output Timing
ø
DREQ0, DREQ1
Figure 22-85 DMAC DREQ Intput Timing
T
2
T T or T
1 2 3
t
t
DRQS
DRQH
T
3
t
DACD2
t
TED