Renesas H8S Series Hardware Manual page 347

Port D Register (PORTD) (On-Chip ROM Version Only)
Bit : 7
PD7
Initial value : —*
R/W : R
Note: * Determined by state of pins PD
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port
D pins (PD to PD ) must always be performed on PDDR.
7 0
If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed
while PDDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and
PDDR are initialized. PORTD retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port D MOS Pull-Up Control Register (PDPCR) (On-Chip ROM Version Only)
Bit : 7
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
Initial value : 0
R/W : R/W
Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an
individual bit basis.
When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bit to 1 turns on the
MOS input pull-up for the corresponding pin.
PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
6 5 4
PD6 PD5 PD4
—* —* —*
R R R
to PD .
7 0
6 5 4
0 0 0
R/W R/W R/W
3 2 1
PD3 PD2 PD1
—* —* —*
R R R
3 2 1
0 0 0
R/W R/W R/W
Rev.6.00 Oct.28.2004 page 319 of 1016
0
PD0
—*
R
0
0
R/W
REJ09B0138-0600H