Renesas H8S Series Hardware Manual page 256

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7-31 shows an example of DREQ pin falling edge activated single address mode transfer.
Address bus
DMA control
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7-31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling
for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle
ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
Rev.6.00 Oct.28.2004 page 228 of 1016
REJ09B0138-0600H
Bus release
ø
DREQ
DACK
Idle
Channel
Request
Minimum of
2 cycles
[1] [2]
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of ø, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts.
When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.)
DMA single Bus release
Transfer source/
destination
Single Idle
Request clear
Request
period
Minimum of
2 cycles
[3] [4] [5] [6]
Acceptance resumes
DMA single Bus release
Transfer source/
destination
Single Idle
Request clear
period
[7]
Acceptance resumes