Block Diagram - Renesas H8S Series Hardware Manual

8.1.2

Block Diagram

Figure 8-1 shows a block diagram of the DTC.
The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1
kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase
processing speed.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt
request
Legend:
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERF:
DTVECR:
Rev.6.00 Oct.28.2004 page 242 of 1016
REJ09B0138-0600H
Interrupt controller DTC
CPU interrupt
request
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to F
DTC vector register
Figure 8-1 Block Diagram of DTC
Internal address bus
Internal data bus
On-chip
RAM