Renesas H8S Series Hardware Manual page 970

TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write
The method for writing to TCSR is different from that for general registers to prevent accidental
overwriting. For details see section 13.2.4, Notes on Register Access.
Note:
Rev.6.00 Oct.28.2004 page 942 of 1016
REJ09B0138-0600H
:
7 6
OVF WT/IT
:
0 0
: *
R/(W) R/W
Timer Enable
0
1
Timer Mode Select
0 Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1
Watchdog timer mode: Generates the WDTOVF signal
TCNT overflows
Notes: 1. The WDTOVF pin function is not available in the
2. For details of the case where TCNT overflows in
Overflow Flag
0 [Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1 [Setting condition]
Set when TCNT overflows from H'FF to H'00 in interval timer mode
Can only be written with 0 for flag clearing.
*
H'FFBC (W), H'FFBC (R)
5 4 3
TME — —
0 1 1
R/W — —
Clock Select
CKS2 CKS1 CKS0
0 0 0 ø/2 (initial value)
1 ø/64
1 0 ø/128
1 ø/512
1 0 0 ø/2,048
1 ø/8,192
1 0 ø/32,768
1 ø/131,072
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
TCNT is initialized to H'00 and halted
TCNT counts
* 2
F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, or
H8S/2390.
watchdog time mode, see section 13.2.3, Reset
Control/Status Register(RSTCSR).
WDT
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
Overflow period*
Clock
(when ø = 20 MHz)
25.6µs
819.2µs
1.6ms
6.6ms
26.2ms
104.9ms
419.4ms
1.68s
*1
when