TMDR5—Timer Mode Register 5
Bit
Initial value
Read/Write
7
6
:
—
—
:
1
1
:
—
—
H'FEA1
5
4
3
—
—
MD3
0
0
0
—
—
R/W
TPU5
2
1
0
MD0
MD2
MD1
0
0
0
R/W
R/W
R/W
Mode
0
0
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
1
0
0
Phase counting mode 1
1
Phase counting mode 2
1
0
Phase counting mode 3
1
Phase counting mode 4
×
×
×
1
—
Note: MD3 is a reserved bit. In a write, it
should always be written with 0.
Rev.6.00 Oct.28.2004 page 861 of 1016
× : Don't care
REJ09B0138-0600H