Basic Instruction Formats; Addressing Modes And Effective Address Calculation; Addressing Mode - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Basic Instruction Formats

The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field

(r), an effective address extension (EA), and a condition field (cc).

Figure 2-9 shows examples of instruction formats.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

(4) Operation field, effective address extension, and condition field

(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on

the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation

(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits.

Some instructions have two register fields. Some have no register field.

(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

(4) Condition Field: Specifies the branching condition of Bcc instructions.

The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all

addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct,

instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Figure 2-9 Instruction Formats (Examples)

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

BRA d:16, etc.

Rev.6.00 Oct.28.2004 page 41 of 1016

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