Renesas H8S Series Hardware Manual page 437

Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-count in the T
TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow.
ø
Address
Write signal
TCNT
TCFV flag
Multiplexing of I/O Pins: In the H8S/2357 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the
TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin
with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a
multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled
before entering module stop mode.
H'FFFF
Prohibited
Figure 10-57 Contention between TCNT Write and Overflow
TCNT write cycle
T T
1 2
TCNT address
M
TCNT write data
Rev.6.00 Oct.28.2004 page 409 of 1016
REJ09B0138-0600H
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