Compare Match Timing - Renesas H8S Series Hardware Manual

12.3.2

Compare Match Timing

Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a
compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the
last state in which the match is true, just before the timer counter is updated.
Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock
input. Figure 12-4 shows this timing.
ø
TCNT
TCOR
Compare match
signal
CMF
Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in
TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle.
Figure 12-5 shows the timing when the output is set to toggle at compare match A.
ø
Compare match A
signal
Timer output pin
Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the
setting of the CCLR1 and CCLR0 bits in TCR. Figure 12-6 shows the timing of this operation.
ø
Compare match
signal
TCNT
N
N
Figure 12-4 Timing of CMF Setting
Figure 12-5 Timing of Timer Output
N
Figure 12-6 Timing of Compare Match Clear
N+1
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Rev.6.00 Oct.28.2004 page 443 of 1016
REJ09B0138-0600H