Renesas H8S Series Hardware Manual page 791

(5) Timing of On-Chip Supporting Modules
Table 22-40 lists the timing of on-chip supporting modules.
Table 22-40 Timing of On-Chip Supporting Modules
= 5.0 V ± 10%, AV
Condition B: V
CC
V = AV
SS
T = –40 to +85°C (wide-range specifications)
a
Condition C: V = 3.0 V to 5.5 V, AV
CC
V = AV
SS
T = –40 to +85°C (wide-range specifications)
a
Item
PORT Output data delay time
Input data setup time
Input data hold time
PPG Pulse output delay time t
TPU Timer output delay time t
Timer input setup time
Timer clock input setup
time
Timer clock
pulse width
TMR Timer output delay time t
Timer reset input setup
time
Timer clock input setup
time
Timer clock
pulse width
SCI Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
= 5.0 V ± 10%, V
CC
= 0 V, ø = 2 to 20 MHz, T
SS
= 3.0 V to 5.5 V, V
CC
= 0 V, ø = 2 to 13 MHz, T
SS
Symbol Min
t
t
t
t
t
Single t
edge
Both t
edges
t
t
Single t
edge
Both t
edges
Asynchro- t
nous
Synchro-
nous
t
t
t
= 4.5 V to AV
ref
= –20 to +75°C (regular specifications),
a
= 3.0 V to AV
ref
= –20 to +75°C (regular specifications),
a
Condition B
Max
— 50
PWD
30 —
PRS
30 —
PRH
— 50
POD
— 50
TOCD
30 —
TICS
30 —
TCKS
1.5 —
TCKWH
2.5 —
TCKWL
— 50
TMOD
30 —
TMRS
30 —
TMCS
1.5 —
TMCWH
2.5 —
TMCWL
4 —
Scyc
6 —
0.4 0.6
SCKW
— 1.5
SCKr
— 1.5
SCKf
,
CC
,
CC
Condition C
Test
Min Max Unit Conditions
— 75 ns Figure 22-86
50 —
50 —
— 75 ns Figure 22-87
— 75 ns Figure 22-88
50 —
50 — ns Figure 22-89
1.5 — t
cyc
2.5 —
— 75 ns Figure 22-90
50 — ns Figure 22-92
50 — ns Figure 22-91
1.5 — t
cyc
2.5 —
4 — t Figure 22-94
cyc
6 —
0.4 0.6 t
Scyc
— 1.5 t
cyc
— 1.5
Rev.6.00 Oct.28.2004 page 763 of 1016
REJ09B0138-0600H