Basic Timing - Renesas H8S Series Hardware Manual

6.5.6

Basic Timing

Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic
bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the
number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the
DRAM access cycle.
The 4 states of the basic timing consist of one T
(column address output cycle) states, T
Read
Write
Note: n = 2 to 5
Rev.6.00 Oct.28.2004 page 140 of 1016
REJ09B0138-0600H
(precharge cycle) state, one T
p
and T .
c1 c2
T
p
ø
A to A
23 0
CSn, (RAS)
CAS, LCAS
HWR, (WE)
D to D
15 0
HWR, (WE)
D to D
15 0
Figure 6-15 Basic Access Timing
(row address output cycle), and two T
r
T T
r c1
Row Column
T
c2
c