Renesas H8S Series Hardware Manual page 980

TIOR0H—Timer I/O Control Register 0H
Bit :
Initial value :
Read/Write :
TGR0B I/O Control
0 0
1
1 0
1
Note: *
When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as the TCNT1 count clock, this setting is invalid and
input capture is not generated.
Rev.6.00 Oct.28.2004 page 952 of 1016
REJ09B0138-0600H
7 6 5
IOB3 IOB2 IOB1 IOB0
0 0
0
R/W R/W R/W R/W
0 0
TGR0B Output disabled
is output
1 Initial output is
compare
0 output
register
1 0
1
0 0 Output disabled
Initial output is
1
0 output
1 0
1
0 0 TGR0B
Capture input
is input
source is
1
capture
TIOCB0 pin
register
×
1
× ×
Capture input
source is channel
1/count clock
H'FFD2
4 3 2 1
IOA3 IOA2 IOA1
0 0 0 0
R/W R/W R/W
TGR0A I/O Control
0 0 0 0
TGR0A Output disabled
is output
1 Initial output is
compare
0 output
register
1 0
1
1 0 0
Output disabled
1 Initial output is
1 output
1 0
1
1 0 0 0 TGR0A
Capture input
is input
source is
1
capture
TIOCA0 pin
register
×
1
× ×
1
Capture input
source is channel
1/count clock
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down*
× : Don't care
TPU0
0
IOA0
0
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
× : Don't care