Renesas H8S Series Hardware Manual page 890

TIOR5—Timer I/O Control Register 5
Bit :
Initial value :
Read/Write :
Rev.6.00 Oct.28.2004 page 862 of 1016
REJ09B0138-0600H
7 6 5
IOB3 IOB2 IOB1
0 0 0
R/W R/W R/W
TGR5B I/O Control
0 0 0 0 TGR5B Output disabled
is output
Initial output is 0
1
compare
output
register
1 0
1
1 0 0
Output disabled
1
Initial output is 1
output
1 0
1
×
1 0 0
TGR5B Capture input
is input source is TIOCB5
1
capture pin
× register
1
H'FEA2
4 3 2 1
IOB0 IOA3 IOA2 IOA1
0 0 0 0
R/W R/W R/W R/W
TGR5A I/O Control
0 0 0 0
TGR5A Output disabled
is output
1 Initial output is 0
compare
output
register
1 0
1
1 0 0
Output disabled
1
Initial output is 1
output
1 0
1
×
1 0 0
TGR5A Capture input
is input source is TIOCA5
1
capture pin
×
register
1
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
TPU5
0
IOA0
0
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
× : Don't care
× : Don't care