Timing Of Overflow Flag (Ovf) Setting; Operation With Cascaded Connection; 16-Bit Counter Mode; Figure 12.8 Timing Of Clearance By External Reset - Renesas H8S/2368 Series Hardware Manual

φ
External reset
input pin
Clear signal
TCNT
12.5.6

Timing of Overflow Flag (OVF) Setting

The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.9
shows the timing of this operation.
φ
TCNT
Overflow signal
OVF
12.6

Operation with Cascaded Connection

If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
12.6.1

16-Bit Counter Mode

When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
N–1

Figure 12.8 Timing of Clearance by External Reset

H'FF

Figure 12.9 Timing of OVF Setting

N H'00
H'00
Rev. 2.00, 05/03, page 485 of 820