Renesas H8S Series Hardware Manual page 143

Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request
signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a
refresh request is generated.
Bit 6
BREQOE
0
1
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF*
or external addresses.
Bit 5
EAE
0
1
Notes: 1. Reserved areas should not be accessed.
2. Addresses H'010000 to H'01FFFF are in the H8S/2357. Addresses H'010000 to H'03FFFF are in the H8S/2398.
Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface.
LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input cannot be used when
LCAS signal is used.
Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface.
Bit 3
DDS
0
1
Bit 2—Reserved: Only 1 should be written to this bit.
Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write
cycle or DMAC single address cycle.
Bit 1
WDBE
0
1
Description
BREQO output disabled. BREQO can be used as I/O port.
BREQO output enabled.
Description
Addresses H'010000 to H'01FFFF*
Addresses H'010000 to H'01FFFF*
1
or a reserved area* (single-chip mode)
Description
When DMAC single address transfer is performed in DRAM space, full access is
always executed
DACK signal goes low from T
Burst access is possible when DMAC single address transfer is performed in DRAM
space
DACK signal goes low from T
Description
Write data buffer function not used
Write data buffer function used
2
are in on-chip ROM
2
are external addresses (external expansion mode)
or T cycle
r 1
or T cycle
c1 2
(Initial value)
2
are to be internal addresses
(Initial value)
(Initial value)
(Initial value)
Rev.6.00 Oct.28.2004 page 115 of 1016
REJ09B0138-0600H