Renesas H8S Series Hardware Manual page 902

MCR—Memory Control Register
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 874 of 1016
REJ09B0138-0600H
: 7 6 5
TPC BE RCDM
: 0 0 0
: R/W R/W R/W
RAS/CS Down Mode
0
1
Burst Access Enable
0 Burst disabled (always full access)
1
For DRAM space access, access in fast page mode
TP Cycle Control
0 1-state precharge cycle is inserted
1
2-state precharge cycle is inserted
H'FED6
4 3 2
CW2 MXC1 MXC0
0 0 0
R/W R/W R/W
Multiplex Shift Count
0 0 8-bit shift
1 9-bit shift
1 0 10-bit shift
1 —
2-CAS Method Select
0 16-bit DRAM space selected
1 8-bit DRAM space selected
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
Bus Controller
1 0
RLW1 RLW0
0 0
R/W R/W
Refresh Cycle Wait Control
0 0 No wait state inserted
1 1 wait state inserted
1 0 2 wait states inserted
1 3 wait states inserted