Dmac Multi-Channel Operation - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Table of Contents

Internal address

Internal read signal

External address

Figure 7-34 Example of Single Address Transfer Using Write Data Buffer Function

When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts

the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single

address transfer.

DMAC Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7-13 summarizes the

priority order for DMAC channels.

Table 7-13 DMAC Channel Priority Order

Short Address Mode

Full Address Mode

Rev.6.00 Oct.28.2004 page 231 of 1016

REJ09B0138-0600H