Renesas H8S Series Hardware Manual page 182

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the
start of the write cycle.
Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a
long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs
in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Rev.6.00 Oct.28.2004 page 154 of 1016
REJ09B0138-0600H
Bus cycle A Bus cycle B
T T T T T
1 2 3 1
Long output
floating time
(a) Idle cycle not inserted
(ICIS0 = 0)
Figure 6-32 Example of Idle Cycle Operation (2)
2
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Data
collision
Bus cycle A Bus cycle B
T T T T T
1 2 3 I 1
(b) Idle cycle inserted
(Initial value ICIS0 = 1)
T
2