Block Diagram - Renesas H8S Series Hardware Manual

7.1.2

Block Diagram

A block diagram of the DMAC is shown in figure 7-1.
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Legend:
DMAWER:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
Rev.6.00 Oct.28.2004 page 166 of 1016
REJ09B0138-0600H
Control logic
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Data buffer
DMA write enable register
DMA terminal control register
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Executive transfer counter register
Figure 7-1 Block Diagram of DMAC
Internal address bus
Address buffer
Processor
MAR0A
MAR0B
MAR1A
MAR1B
Internal data bus
IOAR0A
ETCR0A
IOAR0B
ETCR0B
IOAR1A
ETCR1A
IOAR1B
ETCR1B