Renesas H8S Series Hardware Manual page 903

DRAMCR—DRAM Control Register
Bit
Initial value
Read/Write
RTCNT—Refresh Timer Counter
Bit
Initial value
Read/Write
: 7 6
RFSHE RCW RMODE
: 0 0
: R/W R/W
Refresh Mode
0
1
RAS-CAS Wait
0 Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T
One wait state inserted in CAS-before-RAS refreshing
1
RAS falls in T
Refresh Control
0 Refresh control is not performed
1 Refresh control is performed
: 7 6
: 0 0
: R/W R/W
H'FED7
5 4 3
CMF CMIE
0 0 0
R/W R/W R/W
Refresh Counter Clock Select
Compare Match Interrupt Enable
0 Interrupt request (CMI) by CMF flag disabled
1 Interrupt request (CMI) by CMF flag enabled
Compare Match Flag
0
[Clearing condition]
Cleared by reading the CMF flag when CMF = 1, then
writing 0 to the CMF flag
1
[Setting condition]
Set when RTCNT = RTCOR
DRAM interface: CAS-before-RAS refreshing used
Self-refreshing used
cycle
Rr
cycle
Rc1
H'FED8
5 4
0 0
R/W R/W
Internal clock count value
Bus Controller
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
0 0 0 Count operation disabled
1 Count uses ø/2
1 0 Count uses ø/8
1 Count uses ø/32
1 0 0 Count uses ø/128
1 Count uses ø/512
1 0 Count uses ø/2048
1 Count uses ø/4096
Bus Controller
3 2 1
0 0 0
R/W R/W R/W
Rev.6.00 Oct.28.2004 page 875 of 1016
0
0
R/W
REJ09B0138-0600H