Renesas H8S Series Hardware Manual page 323

Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 5 Data Register (P5DR)
Bit : 7
—
Initial value :
Undefined Undefined Undefined Undefined
R/W : —
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 5 Register (PORT5)
Bit : 7
—
Initial value :
Undefined Undefined Undefined Undefined
R/W : —
Note: * Determined by state of pins P5
PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 5
pins (P5 to P5 ) must always be performed on P5DR.
3 0
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while
P5DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT5 contents are determined by the pin states, as P5DDR and
P5DR are initialized. PORT5 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
6 5 4
— — —
— — —
6 5 4
— — —
— — —
to P5 .
3 0
3 2
P53DR P52DR P51DR
0 0
R/W R/W R/W
3 2
P53 P52 P51
—* —* —*
R R
Rev.6.00 Oct.28.2004 page 295 of 1016
1 0
P50DR
0 0
R/W
to P5 ).
3 0
1 0
P50
—*
R R
REJ09B0138-0600H