Serial Status Register (Ssr) - Renesas H8S Series Hardware Manual

15.2.2

Serial Status Register (SSR)

Bit : 7
TDRE
Initial value : 1
R/W : R/(W)*
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2,
TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR).
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back
from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode.
Bit 4
ERS
0
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR).
However, the setting conditions for the TEND bit, are as shown below.
Bit 2
TEND
0
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
6 5
RDRF ORER
0 0
R/(W)* R/(W)*
Description
[Clearing conditions]
•
Upon reset, and in standby mode or module stop mode
•
When 0 is written to ERS after reading ERS = 1
[Setting condition]
When the low level of the error signal is sampled
Description
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
•
Upon reset, and in standby mode or module stop mode
•
When the TE bit in SCR is 0 and the ERS bit is also 0
•
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character when GM = 0
•
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1
4 3 2
ERS PER TEND
0 0 1
R/(W)* R/(W)* R
1 0
MPB MPBT
0 0
R R/W
(Initial value)
(Initial value)
Rev.6.00 Oct.28.2004 page 521 of 1016
REJ09B0138-0600H