Interface To Bus Master; Operation; Single Mode (Scan = 0) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Interface to Bus Master

ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the

bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).

A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the

CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are

transferred to the CPU.

When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if

only the lower byte is read, incorrect data may be obtained.

Figure 16-2 shows the data flow for ADDR access.

The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode

and scan mode.

Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when

the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D

conversion, and is automatically cleared to 0 when conversion ends.

Rev.6.00 Oct.28.2004 page 546 of 1016

REJ09B0138-0600H

Upper byte read

Bus interface

Lower byte read

Bus interface

Figure 16-2 ADDR Access Operation (Reading H'AA40)

Module data bus

Module data bus

(n = A to D)