Renesas H8S Series Hardware Manual page 967

TCR0—Time Control Register 0
TCR1—Time Control Register 1
Bit :
Initial value :
Read/Write :
7 6 5
CMIEB CMIEA OVIE CCLR1
0 0 0
R/W R/W R/W
Counter Clear
Timer Overflow Interrupt Enable
0 OVF interrupt requests (OVI) are disabled
1 OVF interrupt requests (OVI) are enabled
Compare Match Interrupt Enable A
0 CMFA interrupt requests (CMIA) are disabled
1 CMFA interrupt requests (CMIA) are enabled
Compare Match Interrupt Enable B
0 CMFB interrupt requests (CMIB) are disabled
1 CMFB interrupt requests (CMIB) are enabled
H'FFB0
H'FFB1
4 3 2
CCLR0 CKS2 CKS1
0 0 0
R/W R/W R/W R/W
Clock Select
0 0
1
1 0
1
Note: * If the count input of channel 0 is the TCNT1 overflow
signal and that of channel 1 is the TCNT0 compare
match signal, no incrementing clock is generated.
Do not use this setting.
0 0 Clear is disabled
1 Clear by compare match A
1 0 Clear by compare match B
1 Clear by rising edge of external reset input
8-Bit Timer Channel 0
8-Bit Timer Channel 1
1 0
CKS0
0 0
R/W
0 Clock input disabled
Internal clock: counted at falling edge
1
of ø/8
Internal clock: counted at falling edge
0
of ø/64
Internal clock: counted at falling edge
1
of ø/8192
0 For channel 0:
Count at TCNT1 overflow signal*
For channel 1:
Count at TCNT0 compare match A*
External clock: counted at rising edge
1
External clock: counted at falling edge
0
1 External clock: counted at both rising and
falling edges
Rev.6.00 Oct.28.2004 page 939 of 1016
REJ09B0138-0600H