Renesas H8S Series Hardware Manual page 163

ø
Address bus
CSn
AS
RD
D to D
Read
15 8
D to D
7 0
HWR
LWR
Write
D to D
15 8
D to D
7 0
Note: n = 0 to 7
Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
Bus cycle
T T
1 2
Valid
Valid
T
3
Valid
Valid
Rev.6.00 Oct.28.2004 page 135 of 1016
REJ09B0138-0600H