Renesas H8S Series Hardware Manual page 771

T
ø
A to A
23 0
CS5 to CS2
(RAS)
CAS
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
T
ø
CS5 to CS2
(RAS)
CAS
Figure 22-76 CAS-Before-RAS Refresh Timing
T
p
r
t
AD
t t
AS AH
t
PCH
t
CSD2
Figure 22-75 DRAM Bus Timing
T
Rp
Rr
t
CSD2
t
CSR
t
CASD
T T
C1
t
AD
t
ACC4
t t
CASD ACC1
t
ACC3
t
WRD2
t
t
WCS
WCH
t
t
WDD
WDS
T T
Rc1
Rev.6.00 Oct.28.2004 page 743 of 1016
C2
t
CSD3
t
CASD
t
t
RDS
RDH
t
WRD2
t
WDH
Rc2
t
CSD1
t
CASD
REJ09B0138-0600H