Timer Synchro Register (Tsyr) - Renesas H8S Series Hardware Manual

Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT.
Bit n
CSTn
0
1
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the
TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin
output level will be changed to the set initial output value.
10.2.9

Timer Synchro Register (TSYR)

Bit : 7
—
Initial value : 0
R/W : —
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0
to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or
synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*
counter clearing on another channel*
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means
of bits CCLR2 to CCLR0 in TCR.
Bit n
SYNCn
0
1
Description
TCNTn count operation is stopped
TCNTn performs count operation
6 5
— SYNC5
0 0
— R/W
2
are possible.
Description
TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
4 3
SYNC4 SYNC3 SYNC2
0 0
R/W R/W R/W
2 1 0
SYNC1 SYNC0
0 0 0
R/W R/W
1
, and synchronous clearing through
Rev.6.00 Oct.28.2004 page 367 of 1016
(Initial value)
n = 5 to 0
(Initial value)
n = 5 to 0
REJ09B0138-0600H