Renesas H8S Series Hardware Manual page 952

SSR1—Serial Status Register 1
Bit :
Initial value :
Read/Write :
Transmit Data Register Empty
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Note: * Can only be written with 0 for flag clearing.
Rev.6.00 Oct.28.2004 page 924 of 1016
REJ09B0138-0600H
7 6 5 4
TDRE RDRF ORER FER
1 0 0 0
R/(W)* R/(W)* R/(W)* R/(W)*
Framing Error
0 [Clearing condition]
When 0 is written to FER after reading FER = 1
1 [Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data when reception ends, and the stop bit is 0
Overrun Error
0
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
H'FF84
3 2 1
PER TEND MPB
0 1 0
R/(W)* R R
Multiprocessor Bit Transfer
0
1
Multiprocessor Bit
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
1
[Setting condition]
When data with a 1 multiprocessor bit is received
Transmit End
0
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt
and write data to TDR
1 [Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte
serial transmit character
Parity Error
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
SCI1
0
MPBT
0
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted