Renesas H8S Series Hardware Manual page 739

Item
WR hold time
CAS setup time
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus-floating time
BREQO delay time
ø
A to A
23 0
CS7 to CS0
AS
RD
(read)
D to D
15
(read)
HWR, LWR
(write)
D to D
15
(write)
Figure 22-40 Basic Bus Timing (Two-State Access)
Symbol Min
0.5 ×
t
WCH
t – 10
cyc
0.5 ×
t
CSR
t – 10
cyc
t 30
WTS
t 5
WTH
t 30
BRQS
t —
BACD
t —
BZD
t —
BRQOD
T
1
t
AD
t
AS
t
CSD1
t
ASD
t
RSD1
t
AS
t
0
t
WRD2
t
AS
t
WDD
0
Condition
Max Unit
— ns
— ns
— ns
— ns
— ns
15 ns
50 ns
30 ns
T
2
t
AH
t
ASD
t
t
RSD2
ACC2
t t
RDS
RDH
ACC3
t
WRD2
t
AH
t
t
WSW1
WDH
Rev.6.00 Oct.28.2004 page 711 of 1016
Test
Conditions
Figure 22-40 to
Figure 22-47
Figure 22-44
Figure 22-42
Figure 22-48
Figure 22-49
REJ09B0138-0600H