6.4.5
Wait Control ................................................................................................................................................136
6.5
DRAM Interface....................................................................................................................................................... 138
6.5.1
Overview ..................................................................................................................................................... 138
6.5.2
Setting DRAM Space ..................................................................................................................................138
6.5.3
Address Multiplexing ..................................................................................................................................138
6.5.4
Data Bus ......................................................................................................................................................138
6.5.5
Pins Used for DRAM Interface ................................................................................................................... 139
6.5.6
Basic Timing ............................................................................................................................................... 140
6.5.7
Precharge State Control............................................................................................................................... 141
6.5.8
Wait Control ................................................................................................................................................141
6.5.9
Byte Access Control ....................................................................................................................................143
6.5.10 Burst Operation ........................................................................................................................................... 144
6.5.11 Refresh Control ........................................................................................................................................... 147
6.6
6.6.1
When DDS = 1 ............................................................................................................................................149
6.6.2
When DDS = 0 ............................................................................................................................................150
6.7
Burst ROM Interface ................................................................................................................................................150
6.7.1
Overview ..................................................................................................................................................... 150
6.7.2
Basic Timing ............................................................................................................................................... 151
6.7.3
Wait Control ................................................................................................................................................152
6.8
Idle Cycle..................................................................................................................................................................153
6.8.1
Operation ..................................................................................................................................................... 153
6.8.2
Usage Notes................................................................................................................................................. 155
6.8.3
Pin States in Idle Cycle ............................................................................................................................... 157
6.9
Write Data Buffer Function ......................................................................................................................................158
6.10 Bus Release............................................................................................................................................................... 159
6.10.1 Overview ..................................................................................................................................................... 159
6.10.2 Operation ..................................................................................................................................................... 159
6.10.4 Transition Timing........................................................................................................................................161
6.10.5 Usage Note ..................................................................................................................................................161
6.11 Bus Arbitration ......................................................................................................................................................... 162
6.11.1 Overview ..................................................................................................................................................... 162
6.11.2 Operation ..................................................................................................................................................... 162
6.11.3 Bus Transfer Timing ................................................................................................................................... 163
Section 7 DMA Controller................................................................................................................165
7.1
Overview................................................................................................................................................................... 165
7.1.1
Features ....................................................................................................................................................... 165
7.1.2
Block Diagram............................................................................................................................................. 166
7.1.3
Overview of Functions ................................................................................................................................167
7.1.4
Pin Configuration ........................................................................................................................................169
7.1.5
Register Configuration ................................................................................................................................170
7.2
7.2.1
7.2.2
I/O Address Register (IOAR)......................................................................................................................172
7.2.3
7.2.4
DMA Control Register (DMACR)..............................................................................................................174
7.2.5
7.3
Rev.6.00 Oct.28.2004 page xii of xxiv
REJ09B0138-0600H