Renesas H8S Series Hardware Manual page 158

16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit
access space is accessed, the upper half (D
D ) for the odd address.
0
Wait states cannot be inserted.
Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
Rev.6.00 Oct.28.2004 page 130 of 1016
REJ09B0138-0600H
to D ) of the data bus is used for the even address, and the lower half (D
15 8
ø
Address bus
CSn
AS
RD
D to D
Read
15 8
D to D
7 0
HWR
LWR
Write
D to D
15 8
D to D
7 0
Note: n = 0 to 7
Bus cycle
T T
1 2
Valid
Invalid
High
Valid
High impedance
to
7