Renesas H8S Series Hardware Manual page 882

TSR3—Timer Status Register 3
Bit :
Initial value :
Read/Write :
Note: * Can only be written with 0 for flag clearing.
TCNT3—Timer Counter 3
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 854 of 1016
REJ09B0138-0600H
H'FE85
7 6 5 4
— — — TCFV
1 1 0 0
— — — R/(W)*
Overflow Flag
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
1 [Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
: 15 14 13 12
: 0 0 0 0
: R/W R/W R/W R/W R/W
3
2 1 0
TGFD TGFC TGFB TGFA
0 0 0 0
R/(W)* R/(W)* R/(W)* R/(W)*
Input Capture/Output Compare Flag A
0
1
Input Capture/Output Compare Flag B
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
1 [Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input capture
register
Input Capture/Output Compare Flag C
0 [Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in
DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
1 [Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
register
• When TCNT value is transferred to TGRC by input capture signal
while TGRC is functioning as input capture register
Input Capture/Output Compare Flag D
0 [Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC
is 0
• When 0 is written to TGFD after reading TGFD = 1
1 [Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
H'FE86
11 10 9 8 7
0 0 0 0 0
R/W R/W R/W R/W
Up-counter
TPU3
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
• When DMAC is activated by TGIA interrupt while
DTA bit of DMABCR in DMAC is 1
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT=TGRA while TGRA is function-
ing as output compare register
• When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning as
input capture register
TPU3
6 5 4 3 2
0 0 0 0 0
R/W R/W R/W R/W R/W
1 0
0 0
R/W R/W