Renesas H8S Series Hardware Manual page 173

16-bit single-chip microcomputer
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RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space
is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the
access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again.
• RAS down mode
To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space
is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row
address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6-
21 shows an example of the timing in RAS down mode.
Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode.
A
to A
23
CSn, (RAS)
CAS, LCAS
D
to D
15
Note: n = 2 to 5
DRAM access
T
T
p
r
ø
0
0
Figure 6-21 Example of Operation Timing in RAS Down Mode
External space
access
T
T
T
c1
c2
1
DRAM access
T
T
T
2
c1
c2
Rev.6.00 Oct.28.2004 page 145 of 1016
REJ09B0138-0600H

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