Renesas H8S Series Hardware Manual page 766

16-bit single-chip microcomputer
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(3) Bus Timing
Table 22-28 lists the bus timing.
Table 22-28 Bus Timing
Condition A: V
= 2.7 to 5.5 V, AV
CC
V
= AV
SS
T
= –40 to +85°C (wide-range specifications)
a
= 5.0 V ± 10%, AV
Condition B: V
CC
V
= AV
SS
T
= –40 to +85°C (wide-range specifications)
a
Condition C: V
= 3.0 to 5.5 V, AV
CC
V
= AV
SS
T
= –40 to +85°C (wide-range specifications)
a
Item
Address delay time
Address setup time
Address hold time
Precharge time
CS delay time 1
CS delay time 2
CS delay time 3
AS delay time
RD delay time 1
RD delay time 2
CAS delay time
Read data setup time t
Read data hold time
Read data access
time 1
Read data access
time 2
Read data access
time 3
Read data access
time 4
Read data access
time 5
WR delay time 1
WR delay time 2
WR pulse width 1
Rev.6.00 Oct.28.2004 page 738 of 1016
REJ09B0138-0600H
= 2.7 to 5.5 V, V
CC
= 0 V, ø = 2 to 10 MHz, T
SS
= 5.0 V ± 10%, V
CC
= 0 V, ø= 2 to 20 MHz, T
SS
= 3.0 to 5.5 V, V
CC
= 0 V, ø = 2 to 13 MHz, T
SS
Condition A
Symbol Min
t
AD
0.5 ×
t
AS
t
– 30
cyc
0.5 ×
t
AH
t
– 20
cyc
1.5 ×
t
PCH
t
– 40
cyc
t
CSD1
t
CSD2
t
CSD3
t
ASD
t
RSD1
t
RSD2
t
CASD
30
RDS
t
0
RDH
t
ACC1
t
ACC2
t
ACC3
t
ACC4
t
ACC5
t
WRD1
t
WRD2
1.0 ×
t
WSW1
t
– 40
cyc
= 2.7 V to AV
ref
= –20 to +75°C (regular specifications),
a
= 4.5 V to AV
ref
= –20 to +75°C (regular specifications),
a
= 3.0 V to AV
ref
= –20 to +75°C (regular specifications),
a
Condition B
Max
Min
Max
40
20
0.5 ×
t
– 15
cyc
0.5 ×
t
– 10
cyc
1.5 ×
t
– 20
cyc
40
20
40
20
40
25
40
20
40
20
40
20
40
20
15
0
1.0 ×
1.0 ×
t
– 50
t
– 25
cyc
cyc
1.5 ×
1.5 ×
t
– 50
t
– 25
cyc
cyc
2.0 ×
2.0 ×
t
– 50
t
– 25
cyc
cyc
2.5 ×
2.5 ×
t
– 50
t
– 25
cyc
cyc
3.0 ×
3.0 ×
t
– 50
t
– 25
cyc
cyc
40
20
40
20
1.0 ×
t
– 20
cyc
,
CC
,
CC
,
CC
Condition C
Min
Max
Unit Conditions
40
ns
0.5 ×
ns
t
– 30
cyc
0.5 ×
ns
t
– 20
cyc
1.5 ×
ns
t
– 40
cyc
40
ns
40
ns
40
ns
40
ns
40
ns
40
ns
40
ns
30
ns
0
ns
1.0 ×
ns
t
– 50
cyc
1.5 ×
ns
t
– 50
cyc
2.0 ×
ns
t
– 50
cyc
2.5 ×
ns
t
– 50
cyc
3.0 ×
ns
t
– 50
cyc
40
ns
40
ns
1.0 ×
ns
t
– 40
cyc
Test
Figure 22-72
to
Figure 22-79

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