Renesas H8S Series Hardware Manual page 382

Bit 7
Channel IOB3
2 0
1
Bit 7
Channel IOB3
3 0
1
Note: When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is
*
invalid and input capture is not generated.
Rev.6.00 Oct.28.2004 page 354 of 1016
REJ09B0138-0600H
Bit 6 Bit 5 Bit 4
IOB2 IOB1 IOB0 Description
0 0 0 TGR2B is Output disabled
output
1
compare
0
1
register
1
1 0 0
1
1 0
1
×
0 0 TGR2B is
input
1
capture
×
1
register
Bit 6 Bit 5 Bit 4
IOB2 IOB1 IOB0 Description
0 0 0 TGR3B is Output disabled
output
1
compare
0
1
register
1
1 0 0
1
1 0
1
0 0 0 TGR3B is
input
1
capture
×
1
register
× ×
1
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCB2 pin
Input capture at both edges
Initial output is 0 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Output disabled
Initial output is 1 0 output at compare match
output
1 output at compare match
Toggle output at compare
match
Capture input Input capture at rising edge
source is
Input capture at falling edge
TIOCB3 pin
Input capture at both edges
Capture input Input capture at TCNT4
source is channel count-up/count-down*
4/count clock
(Initial value)
×: Don't care
(Initial value)
×: Don't care