Renesas H8S Series Hardware Manual page 247

Full Address Mode (Cycle Steal Mode): Figure 7-20 shows a transfer example in which TEND output is enabled and
word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external
16-bit, 2-state access space.
ø
Address bus
RD
HWR
LWR
TEND
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus
cycle is inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
DMA DMA
read write
Bus release Bus release
Figure 7-20 Example of Full Address Mode (Cycle Steal) Transfer
DMA DMA DMA
read write read
Bus release
DMA DMA
write dead
Last transfer Bus
cycle release
Rev.6.00 Oct.28.2004 page 219 of 1016
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