Register Descriptions; Timer Counters 0 And 1 (Tcnt0, Tcnt1); Time Constant Registers A0 And A1 (Tcora0, Tcora1) - Renesas H8S Series Hardware Manual

12.2

Register Descriptions

12.2.1

Timer Counters 0 and 1 (TCNT0, TCNT1)

Bit : 15 14
Initial value : 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or
external clock source. This clock source is selected by clock select bits CKS2 to CKS0 of TCR. The CPU can read or
write to TCNT0 and TCNT1 at all times.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word transfer instruction.
TCNT0 and TCNT1 can be cleared by an external reset input or by a compare match signal. Which signal is to be used for
clearing is selected by clock clear bits CCLR1 and CCLR0 of TCR.
When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1.
TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode.
12.2.2

Time Constant Registers A0 and A1 (TCORA0, TCORA1)

Bit : 15 14
Initial value : 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA0 and TCORA1 are 8-bit readable/writable registers. TCORA0 and TCORA1 comprise a single 16-bit register so
they can be accessed together by word transfer instruction.
TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag of
TCSR is set. Note, however, that comparison is disabled during the T
The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 of TCSR.
TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.
Rev.6.00 Oct.28.2004 page 436 of 1016
REJ09B0138-0600H
TCNT0
13 12 11 10 9
0 0 0 0 0
TCORA0
13 12 11 10 9
1 1 1 1 1
TCNT1
8 7 6 5 4
0 0 0 0 0
TCORA1
8 7 6 5 4
1 1 1 1 1
state of a TCOR write cycle.
2
3 2 1 0
0 0 0 0
3 2 1 0
1 1 1 1