Renesas H8S Series Hardware Manual page 876

MRB—DTC Mode Register B
Bit
Initial value
Read/Write
SAR—DTC Source Address Register
Bit
Initial value
Read/Write
DAR—DTC Destination Address Register
Bit
Initial value
Read/Write
CRA—DTC Transfer Count Register A
Bit
Initial value
Read/Write
Rev.6.00 Oct.28.2004 page 848 of 1016
REJ09B0138-0600H
: 7 6
CHNE DISEL
: Undefined Undefined
: — —
DTC Interrupt Select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1
After a data transfer ends, the CPU interrupt is enabled
DTC Chain Transfer Enable
0 End of DTC data transfer
1 DTC chain transfer
:
23 22 21 20
:
Unde- Unde- Unde- Unde-
fined fined fined fined
: — — — —
: 23 22 21 20
Unde- Unde- Unde- Unde- Unde-
:
fined fined fined fined
— — — —
:
: 15 14 13 12
:
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined
:
— — — —
CRAH
Specifies the number of DTC data transfers
H'F800—H'FBFF
5 4
— — —
Undefined Undefined Undefined
— — —
H'F800—H'FBFF
19 - - -
- - -
Unde-
- - -
fined
—
- - -
Specifies transfer data source address
H'F800—H'FBFF
19 - - -
- - -
- - -
fined
—
- - -
Specifies transfer data destination address
H'F800—H'FBFF
11 10 9 8 7
Unde- Unde- Unde- Unde-
fined fined fined fined fined
— — — — —
DTC
3 2 1
— —
Undefined Undefined
— —
Reserved
Only 0 should be written to these bits
DTC
4 3 2
Unde- Unde- Unde-
fined fined fined
— — —
DTC
4 3 2
Unde- Unde- Unde-
fined fined fined
— — —
DTC
6 5 4 3 2
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
— — — — —
CRAL
0
—
Undefined
—
1 0
Unde- Unde-
fined fined
— —
1 0
Unde- Unde-
fined fined
— —
1 0
Unde- Unde-
fined fined
— —