19.15.8 Pin Configuration; 19.15.9 Register Configuration - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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19.15.8 Pin Configuration

The flash memory is controlled by means of the pins shown in table 19-31.

Table 19-31 Flash Memory Pins

Transmit data

Receive data

The registers used to control the on-chip flash memory when enabled are shown in table 19-32.

In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2

(except RAMER).

Table 19-32 Flash Memory Registers

Flash memory control register 1

Flash memory control register 2

Erase block register 1

Erase block register 2

System control register 2

RAM emulation register

Notes: 1. Lower 16 bits of the address.

2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2).

3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid.

4. If a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00.

5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the

access requiring 2 states.

6. The SYSCR2 register can only be used in the F-ZTAT version. In the masked ROM version this register will

return an undefined value if read, and cannot be modified.

Rev.6.00 Oct.28.2004 page 626 of 1016

REJ09B0138-0600H

Abbreviation

Abbreviation R/W

Sets MCU operating mode

Sets MCU operating mode in programmer mode

Serial transmit data output

Serial receive data input

Initial Value