Renesas H8S Series Hardware Manual page 318

P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after
a manual reset*, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and
P3DR specifications.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 3 Data Register (P3DR)
Bit : 7
—
Initial value :
Undefined Undefined
R/W : —
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P3
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 3 Register (PORT3)
Bit : 7
—
Initial value :
Undefined Undefined
R/W : —
Note: * Determined by state of pins P3
PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P3
always be performed on P3DR.
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while
P3DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and
P3DR are initialized. PORT3 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 3 Open Drain Control Register (P3ODR)
Bit : 7
—
Initial value :
Undefined Undefined
R/W : —
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P3
Rev.6.00 Oct.28.2004 page 290 of 1016
REJ09B0138-0600H
6 5 4
— P35DR P34DR
0 0
— R/W R/W
6 5 4
— P35 P34
—* —*
— R R
to P3 .
5 0
6 5 4
— P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
0 0
— R/W R/W
3 2
P33DR P32DR P31DR
0 0
R/W R/W R/W
3 2
P33 P32 P31
—* —* —*
R R
3 2
0 0
R/W R/W R/W
1 0
P30DR
0 0
R/W
to P3 ).
5 0
1 0
P30
—*
R R
1 0
0 0
R/W
to P3
5
to P3 ) must
5 0
).
0