Timing Of Tcnt External Reset; Timing Of Overflow Flag (Ovf) Setting - Renesas H8SX/1650 Hardware Manual

11.5.5

Timing of TCNT External Reset

TCNT is cleared at the rising edge or high level of an external reset input, depending on the
settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states.
Figures 11.10 and 11.11 show the timing of this operation.
P
External reset
input pin
Clear signal
TCNT
Figure 11.10 Timing of Clearance by External Reset (Rising Edge)
P
External reset
input pin
Clear signal
TCNT
Figure 11.11 Timing of Clearance by External Reset (High Level)
11.5.6

Timing of Overflow Flag (OVF) Setting

The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure
11.12 shows the timing of this operation.
P
TCNT
Overflow signal
OVF
N – 1
N – 1
H'FF
Figure 11.12 Timing of OVF Setting
Section 11 8-Bit Timers (TMR)
N H'00
N H'00
H'00
Rev.2.00 Jun. 28, 2007 Page 429 of 666
REJ09B0311-0200